Method and apparatus of a fast digital automatic gain control circuit

ABSTRACT

An automatic gain control circuit with a very wide operational range, less hardware, and faster response, and more flexibility includes a signal strength estimator, a gain adjusting factor device and a multiplier. After the signal strength estimator finds signal strength, the gain adjusting factor device will generate a gain adjusting factor corresponding to the signal strength. Then the multiplier will update gain by multiplying it the gain adjusting factor.

FEDERALLY SPONSORED RESEARCH

[0001] Not Applicable

SEQUENCE LISTING OR PROGRAM

[0002] Not Applicable

FIELD OF THE INVENTION

[0003] The present invention relates to digital automatic gain control(AGC) circuits and, more particularly, to the AGC circuits ofpackage-switched high-speed wireless communication systems.

BACKGROUND

[0004] In wireless communications, due to large variations in receivedsignal power caused by propagation attenuation (e.g., fading due tobuildings or geographic features), a control mechanism referred asautomatic gain control (AGC) has to be used in a receiver to control thegain of the receiving amplifier dynamically so that subsequent sectionscan operate within a desired operating range. These sections includeamplifiers, mixers, analog-to-digital converters (ADC), and basebandanalog or digital processing devices. An AGC circuit is designed to keepthe amplified received signal at a near-constant level over a largedynamic range of received signal power levels. The parameters involvedin designing an AGC circuit include its operational range and itsresponse time.

[0005] In some communication systems, the signal variation can exceed 80to 90 dB in signal power. This wide variation range could be caused byhills or buildings and power control failure occurring when a mobilestation is in close proximity to a base station. It is desirable for anAGC circuit to be able to operate in a very wide range so that thecommunication system can work in many scenarios.

[0006] In package-switched wireless communications, AGC has to setup onevery package. The more time for setting up AGC, the less time availablefor transmitting data. Therefore, the effective data transmission ratewill be reduced. The problem is more obvious and serious when thetransmission rate is very high. With a faster AGC circuit, acommunication system will have more time to transmit data and thereforeincrease its capacity.

[0007] In a wireless communication system, the power consumption is oneof the major concerns. In order to make the communication system to workfor longer time with the same battery, every subsystem including AGCshould consume as less power as possible.

[0008] One technology to make an AGC circuit to have wide operationalranges is given by U.S. Pat. No. 4,263,560, entitled. LOG-EXPONENTIALAGC CIRCUIT, by Dennis W. Ricker. FIG. 1 is a digital implementationdiagram of the AGC based on Ricker's patent.

[0009] The digital AGC circuit shown in FIG. 1, generally denoted by100, utilizes both the logarithmic algorithm and exponential algorithm.The input signal S_(in) is applied to a variable-gain amplifier 110. Theoutput of the variable-gain amplifier is converted into digital signalS_(out) by an ADC device 120. The digital signal S_(out) will be sent todigital envelope detector 130 and other devices such as automaticfrequency control and clock recovery for further processing. The outputof the envelope detector 130 is the envelope of the signal representedby S_(out). This envelope, denoted by X, is applied to a logarithmicdevice 140 with its output connected to the negative terminal of anadder 160. The reference signal level R, after going through alogarithmic device 150, is connected to the positive terminal of adder160. The output of adder 160 is the error signal E. This error signal isapplied to an integrator 170 to filter out the high frequencies of theerror signal. The output of integrator 170, denoted by K, then goesthrough an exponential device 180. The output of exponential device 180is digital gain control signal G. This digital gain control signal isconverted into analog gain control signal by a digital-to-analogconverter (DAC) 190. Finally, the analog gain control signal controlsthe amplification factor of the variable-gain amplifier 110.

[0010] There are some problems with the digital AGC of FIG. 1 when it isapplied in package-switched high-speed wireless communication systems.

[0011] One problem associated with the digital implementation ishardware consuming and time consuming. First, a lot of hardware isneeded to build circuits to approximate both logarithmic function andexponential function. Second, a lot of time is needed for the circuitsto complete the calculation of logarithmic function and exponentialfunction. The more hardware and more time will lead more powerconsumption and reduce effective data rate in package-switchedhigh-speed wireless communications.

[0012] Another problem is associated with signal strength. When theincoming signal is very strong, there is distortion on the output ofvariable-gain amplifier and therefore the output of digital envelopedetector will not correctly reflect the signal strength. In the digitalimplementation, there is an extra problem. The signal after ADC could belimited even if the signal before ADC is not. When the incoming signalis very strong, the output of ADC does not correctly reflect the comingsignal strength due to the operational range limitation of an ADCcircuit. Due to quantisation error of ADC, there is some discrepancybetween input and output of an ADC. When the incoming signal is veryweak, this discrepancy could be very significant considering therelatively small incoming signal.

[0013] Using the notations on FIG. 1, mathematically, one can obtain

E((n+1)T)=1n(R)−1n(X(n+1)T)

K((n+1)T)=K(nT)+α·E((n+1)T)

G((n+1)T)=e ^(K((n+1)T))

[0014] where E is the error signal, R is the reference signal level, Xis the envelope, K is the output of integrator, G is the gain, T is theclock cycle of gain adjustment, the nT is the moment of the nth clockcycle, and α is the adjusting coefficient embedded in the integrator170. α is a positive number and usually much smaller than 1.

[0015] Further, one can derive

G((n+1)T)=G(nT)·(R/X((n+1)T))^(α)

Or

G((n+1)T)=G(nT)·β·(X((n+1)T))^(−α)  (1)

[0016] with β=R^(α).

[0017] Therefore, the gain adjusting factor F is

F=β·X ^(−α)  (2)

SUMMARY OF THE INVENTION

[0018] Due to the features of package-switched high-speed wirelesscommunication systems, it is very important to have a very wide range,power saving, and fast response AGC circuit.

[0019] It is an object of this invention to provide a digital AGCimplementation with wide operational range, fast response time, and lesshardware.

[0020] It is another object of this invention to provide a methodologyto design a digital AGC circuit with a preferred relation between signalstrength and gain adjusting factor.

[0021] It is a further object of this invention to provide a methodologyof AGC to utilize, both current and previous, signal strengths and gainsto update gain.

[0022] It is another object of this invention to provide an AGCstructure that is flexible to update gain in a preferred way.

[0023] It is another object of this invention to provide an AGCstructure that is able to update gain more properly when the incomingsignal is very strong or very weak signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawing figures depict preferred embodiments of the presentinvention by way of example, not by way of limitations.

[0025]FIG. 1 is a prior art AGC circuit with logarithmic and exponentialdevices.

[0026]FIG. 2 is a curve of gain adjusting factor versus signal strength.

[0027]FIG. 3 is an AGC circuit according to an embodiment of the presentinvention.

[0028]FIG. 4 is an approximation of the curve of FIG. 2.

[0029]FIG. 5 shows the reference signal strength and reference gainadjusting factors for the curve of FIG. 4.

[0030]FIG. 6 is an AGC circuit according to another embodiment of thepresent invention.

[0031]FIG. 7 illustrates an implementation of the gain adjusting factordevice shown of FIG. 6.

[0032]FIG. 8 is an AGC circuit according to another embodiment of thepresent invention.

[0033]FIG. 9 is an AGC circuit according to another embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0034]FIG. 2 shows the relation between the estimated signal strengthand the gain adjusting factor for α=0.5 and R=1.0 or β=1.0. When thereference level R and the updating coefficient α in the integrator 170of FIG. 1 have been specified, one can find β=R^(α) and obtain the curveof gain adjusting factor β·X^(−α) versus estimated signal strength X byplotting β·X^(−α). Here the signal strength X is referenced to any kindof physical measurement, which reflects the relative strength of asignal. Signal power and signal envelope are two different forms ofsignal strength. In some real environment, the signal power could varyover 90 dB, however, the interesting signal strength range of FIG. 2 isassumed from 0.1 to 2.0 for simplicity.

[0035]FIG. 3 illustrates a digital AGC circuit according to anembodiment of the present invention. It is a direct implementation ofthe formula (2) without using logarithmic and exponential algorithms.The AGC circuit, generally denoted by 300, is shown in FIG. 3.

[0036] A variable-gain amplifier 310 amplifies the input signal S_(in)by an amplification factor controlled by the analog gain control signalfrom a digital-to-analog converter (DAC) 380. The output of thevariable-gain amplifier 310, which is in analog form, is then convertedinto digital signal S_(out) by an ADC device 320. A signal strengthestimator 330, which is able to extract the strength information from asignal, generates the signal strength X from S_(out). A signal strengthestimator 330 could be an envelope detector, a magnitude moving average,or peak detector with periodical reset.

[0037] When the parameters α and β are given, gain adjusting factordevice 340 will find the gain adjusting factor F according to formula(2) or the relation specified by FIG. 2.

[0038] A multiplier 350 will multiply the gain adjusting factor F withoutput of a delay device 370. The output of multiplier 350 will be sentto a mapping device 360. There are two purposes for the mapping device360. The first purpose is to make sure that the input of multiplier 350will not become zero and that its output will not be overflowed. Thesecond purpose is to make sure that the output of the digital-to-analog(DAC) 380 will be in a proper range to control the variable-gainamplifier 310. In many situations, the mapping device 360 behaviors justlike a regular limiter even through more complex mapping could beapplied.

[0039] The output of the mapping device 360 is sent to a delay device370. The main purpose is to make sure there is at least a delay in theloop consisting of multiplier 350, mapping device 360, and delay device370.

[0040] The output of delay device 370 will be converted into analog gaincontrol signal by the DAC device 380. The analog gain control signalwill then control variable-gain amplifier 310. The output of 370 is alsoconnected to one terminal of multiplier 350.

[0041] Compared to FIG. 1, there is only one exponential device which isembedded in gain adjusting factor device 340 and no logarithmic deviceat all.

[0042] In order to get rid of the exponential device, one canapproximate the curve of FIG. 2 by staircase curve shown in FIG. 4.Basically, the interesting range of signal strength is divided into somesmall intervals and the gain adjusting factor in each small interval isassumed to be constant.

[0043]FIG. 5 expresses the information of FIG. 4 in the form of vectors.The reference signal strengths represent the small intervals on X axis,that is, signal strength axis, and the reference gain adjusting factorsstand for the gain adjusting factors in the corresponding intervals.

[0044] The digital AGC circuit, generally denoted by 600 in FIG. 6 issubstantially similar to the digital AGC circuit in FIG. 3. Thevariable-gain amplifier 610, the ADC device 620, the signal strengthestimator 630, the multiplier 650, the mapping device 660, the delaydevice 670, and the DAC device 680 in FIG. 6 operate in the same manneras the corresponding device of the variable-gain amplifier 310, the ADCdevice 320, the signal strength estimator 330, the multiplier 350, themapping device 360, the delay device 370, and the DAC device 380 in FIG.3.

[0045] The gain adjusting factor device 640 in FIG. 6 differs from thegain adjusting factor device 340 in FIG. 3. First, the gain adjustingfactor device 640 has signal strength, reference signal strengths andreference gain adjusting factors as inputs with both reference signalstrengths and reference gain adjusting factors being vectors. The gainadjusting factor device 340 has signal strength, α and β as input withboth α and β being scalar. Second, instead of calculating the gainadjusting factor directly as the gain adjusting factor device 340 does,the gain adjusting factor device 640 outputs a gain adjusting factor Fwhich depends on which interval the signal strength X falls into. Forexample, when X=1.45, which is larger than 1.4 but smaller than 1.5, andtherefore according to FIG. 5, the gain adjusting factor F could be0.8452.

[0046]FIG. 7 illustrates an implementation of the gain adjusting factordevice 640 shown in FIG. 6. Basically, the comparing logic circuit 641determines among all the intervals represented by reference signalstrength which interval the signal strength X falls into and generatesan index corresponding to that interval. Then the selecting logiccircuit 642 uses this index to select corresponding gain adjustingfactor F from a set of reference gain adjusting factors.

[0047]FIG. 7 shows one way to implement the gain adjusting factor device640. Actually, there are many other ways to implement the gain adjustingfactor device 640. For example, various interpolation methods could beused to generate the gain adjusting factor F.

[0048] It could be noticed that both gain adjusting factor device 640 inFIG. 6 and the gain adjusting factor device 340 in FIG. 3 areimplementations of formula (2) and therefore both digital AGC 300 anddigital AGC 600 can accomplish the function of digital AGC 100. However,they are are not limited to the function of digital AGC 100 because thecurves in FIG. 2 and FIG. 4 could be different from the one specified byformula (2).

[0049] A modified digital AGC, generally denoted as 800, is shown inFIG. 8. The digital AGC 800 is substantially similar to the digital AGCcircuit in FIG. 3. The variable-gain amplifier 810, the ADC device 820,the signal strength estimator 830, the multiplier 850, the mappingdevice 860, the delay device 870, and the DAC device 880 in FIG. 8operate in the same manner as the corresponding device of thevariable-gain amplifier 310, the ADC device 320, the signal strengthestimator 330, the multiplier 350, the mapping device 360, the delaydevice 370, and the DAC device 380 in FIG. 3. The gain adjusting circuit840 generates a gain adjusting factor based on the relation betweensignal strength and gain adjusting factor. The relation could be in manydifferent forms such as a mathematics formula or a curve. Further, thegain adjusting circuit 840 could generate gain adjusting factoraccording to a relation for a particular situation and generate gainadjusting factor according to another relation for another particularsituation.

[0050] It could be also noticed that the digital AGC circuits on FIG. 1,FIG. 3, FIG. 6, and FIG. 8 update gain according to the current gain andthe current signal strength only.

[0051] Another modified digital AGC, generally denoted as AGC 900 isshown in FIG. 9. The variable-gain amplifier 910, the ADC device 920,the signal strength estimator 930, the delay device 970, and the DACdevice 980 in FIG. 9 operate in the same manner as the correspondingdevice of the variable-gain amplifier 310, the ADC device 320, thesignal strength estimator 330, the delay device 370, and the DAC device380 in FIG. 3.

[0052] The gain generating device 950 can update gain according toformula (1). It can also use current signal strength and previous signalstrength provided by memory device 940 and current gain and previousgains provided by memory device 960 to update the gain. Further, thegain generating device 950 can make use of the information from otherportions of the receiver. The information could be whether it is at thebeginning of a new package or in the middle of the current package, howfar the receiver is away from transmitter, and how fast the receiver andtransmitter relatively moves.

[0053] With the information provided by memory devices 940 and 960 aswell as from other portions of the receiver, the digital AGC 900 is ableto update the gain in a more complex and flexible way. For example, thegain generating device 950 could use a channel model corresponding to aparticular circumstance, estimate the most possible signal strength ofthe amplified signal if ADC were perfect, and generate gain dynamicallyaccording to that particular circumstance.

What is claimed is:
 1. An automatic gain control circuit comprising: an amplifier having at least a received signal and an analog gain control signal as separate inputs, wherein the amplifier amplifies the received signal by a amplification factor which is controlled by the analog gain control signal; an analog-to-digital converter configured to convert the amplified signal from analog format to digital format; a signal strength estimator configured to measure the signal strength of the amplified signal; a gain adjusting factor device configured to generate a gain adjusting factor; a multiplier configured to multiply a digital gain control signal by said gain adjusting factor; and a digital-to-analog converter configured to convert a gain control signal from digital format to analog format.
 2. The automatic gain control circuit according to claim 1, further comprising: a mapping device configured to map a signal into a different signal; and a delay device configured to insert some delay for a loop.
 3. The automatic gain control circuit according to claim 1, wherein said gain adjusting factor device contains means for generating a gain adjusting factor based on a predetermined relation between signal strength and gain adjusting factor.
 4. The gain adjusting factor device according to claim 3, wherein said predetermined relation is described by one from the group consisting of a mathematical formula, a curve, and a set of number pairs.
 5. The automatic gain control circuit according to claim 1, wherein said gain adjusting factor device contains means for generating a gain adjusting factor inversely proportional to said signal strength.
 6. The automatic gain control circuit according to claim 1, wherein said gain adjusting factor device has signal strength, a plurality of reference signal strengths, and a plurality of reference gain adjusting factors as input and gain adjusting factor as its output.
 7. The adjusting factor device according to claim 6, further comprising: a comparing logic circuit configured to generate an index according to the measured signal strength; and a selecting logic circuit configured to select a gain adjusting factor from a plurality of gain adjusting factors according to said index.
 8. An automatic gain control circuit, comprising: an amplifier having at least a received signal and an analog gain control signal as separate inputs, wherein the amplifier amplifies the received signal by amplification factor which is controlled by the analog gain control signal; a signal strength estimator configured to measure the strength of the amplified signal; a first memory device configured to store a plurality of signal strengths; a gain generating device configured to generate a gain; and a second memory device configured to store a plurality of gains.
 9. The automatic gain control circuit according to claim 8, further comprising: an analog-to-digital converter configured to convert the amplified signal from analog format to digital format; a delay device configured to insert some delay; and a digital-to-analog converter configured to convert a gain control signal from digital format to analog format.
 10. The digital automatic gain control circuit according to claim 8, wherein said gain generating device contains means to generate gain by making use of current gain and a number of previous gains.
 11. The digital automatic gain control circuit according to claim 8, wherein said gain generating device contains means to generate gain by making use of current signal strength and a number of previous signal strengths to update gain.
 12. The automatic gain control circuit according to claim 8, wherein said gain generating device contains means for generating gain based on the signal strengths stored on said first memory device and the gains stored on said second memory device update gain.
 13. The automatic gain control circuit according to claim 8, wherein said gain generating device contains means for generating gain dynamically.
 14. The automatic gain control circuit according to claim 8, wherein said gain generating circuit contains means for generating gain differently under different scenarios.
 15. A method for automatically varying a gain control signal for a receiver, comprising the steps of a) amplifying a received signal according to an adjustable amplification factor, wherein the adjustable amplification factor is determined by an analog gain control signal; b) converting the amplified signal from analog to digital format; c) calculating the strength of the amplified signal; d) generating new gain based on previous gains and signal strengths; and e) converting the new gain from digital format into analog format to generate analog gain control signal.
 16. The method according to claim 15, wherein said generating new gain updates gain by multiplying it with a gain adjusting factor.
 17. The method according to claim 16, wherein said gain adjusting factor generates a gain adjusting factor based on a mathematics formula describing the relation between signal strength and gain adjusting factor.
 18. The method according to claim 16, wherein said gain adjusting factor generates a gain adjusting factor based on a set of number pairs describing the relation between signal strength and gain adjusting factor.
 19. The method according to claim 15, wherein said generating new gain produces gain based on the relation of new gain versus current signal strength and current gain.
 20. The method according to claim 15, wherein said generating new gain creates gain based on the relation of new gain versus current and previous signal strengths and current and previous gains. 